1. Field of the Invention
The present invention relates to a time-to-digital converter (TDC), and more specifically, to a TDC having a small circuit scale and high resolution.
2. Related Art
Recently, the performance of AD converters has improved remarkably and there is a demand for the detection of the accuracy of control signals that serve as a reference for operation, for example, the detection of jitters and periodic errors, with high precision. As a circuit to detect phase (jitter) with respect to the reference clock of a signal to be measured, which is a control signal, a TDC is widely known.
FIG. 1A is a diagram showing a basic circuit configuration of a conventional TDC and FIG. 1B is a time chart showing the circuit operation of the conventional TDC in FIG. 1A.
As shown in FIG. 1A, the TDC has a delay circuit line (delay line), in which a plurality of delay elements (non-inverter buffers) 11 that sequentially delay an original clock CK by a predetermined delay amount τ1 are connected in series, a plurality of flip-flops 12 that receive each of delayed clocks CK1, CK2, CK3, . . . , sequentially delayed by the delay line as a data input and a signal SC to be measured as a clock input, and an encoder circuit 13 that calculates a jitter of the signal SC to be measured with respect to the original clock CK 35 from outputs Q1, Q2, Q3, . . . , of the plurality of flip-flops 12.
Non-inverter buffer 11 is realized by, for example, connecting inverters in two stages, or using a circuit described in Japanese Unexamined Patent Publication (Kokai) No. H9-64197. The number of connected non-inverters 11 needs to be greater than or equal to a number calculated by dividing the expected magnitude of the jitter of signal SC to be measured by the delay amount of non-inverter buffer 11 plus a predetermined margin.
As shown in FIG. 1B, delayed clocks CK1, CK2, CK3, . . . , output from each of non-inverter buffers 11 are delayed from one another by a predetermined delay amount. When signal SC to be measured rises, delayed clocks CK1, CK2 before a certain delayed clock are in the “high (H)” state and outputs Q1, Q2 of flip-flop 12 are “H”, however, delayed clocks CK3, . . . , after that are in the “low (L)” state and outputs Q3, . . . , of flip-flop 12 are “L”, and therefore, it is possible to detect the timing at which signal SC to be measured with respect to original clock CK rises by detecting the position at which the output of flip-flop 12 changes using encoder circuit 13. If there is a jitter in the rise of signal SC to be measured, the position at which the output of flip-flop 12 changes is different, and the output of encoder circuit 13 changes as a result.
Documents: J. Jansson, et., “A CMOS Time-to-Digital Converter With Better Than 10 ps Single-shot Precision”, JSSC, Vol. 41, NO. 6, JUNE 2006, and R. Staszewski, et., Digital RF Processor DRP™ for Cellular Phones”, ISSCC, 200 describe the TDC shown in FIG. 1A. The document of R. Staszewski cannot be easily obtained. The contents of this documents are included in R. B. Staszewski, et., “All-Digital Tx Frequency Synthesizer and Discrete-Time Receiver for Bluetooth Radio in 130-nm CMOS”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004.
Document: K. Nose, M, Kajita, M. Mizuno, “A 1 ps-Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling”, IEEE JSSC, vol. 41, no. 12, pp. 2911-2920 (December 2006) describes a TDC in which delay units with the delay amount nτ1 (n is an integer) including a plurality of non-inverter buffers are connected in series, and groups, each of which includes n−1 non-inverter buffers with delay amount τ1 connected in series, are respectively connected at each connection node of the delay units. A circuit of the TDC is formed in a small range.
In the TDC shown in FIG. 1A and the TDC described in document: K. Nose, M, Kajita, M. Mizuno, “A 1 ps-Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling”, IEEE JSSC, vol. 41, no. 12, pp. 2911-2920 (December 2006), the time resolution of the jitter of the measured signal is the delay amount of the non-inverter buffer. As described above, the delay amount of the non-inverter buffer has a limit because it is regulated by a process etc. On the other hand, it is possible to manufacture two kinds of non-inverter buffer with a small difference between delay amounts. For example, although it is difficult to stably manufacture a non-inverter buffer with a delay amount of 2 ps, it is possible to stably manufacture non-inverter buffers with delay amounts of 10 ps and 8 ps (of course variations involved).
Documents: J. Rivoir, “Fully-Digital Time-to-Digital Converter for ATE with Autonomous Calibration”, IEEE International Test Conference, Santa Clara, (October 2006), and J. Rivoir, “Statistical Linearity Calibration of Time-to-Digital Converters Using a Free-Running Ring Oscillator”, 15th Asian Test Symposium (2006) describe the vernier delay line TDC that has improved the time resolution by providing two kinds of delay line in which two kinds of non-inverter buffer with delay amounts slightly different from each other are connected in series, respectively, and by inputting a reference clock to one of them and a signal to be measured to the other and comparing the outputs in the corresponding stages.
FIG. 2 is a diagram showing the configuration and operation of the TDC that has increased the time resolution described in documents: J. Rivoir, “Fully-Digital Time-to-Digital Converter for ATE with Autonomous Calibration”, IEEE International Test Conference, Santa Clara, (October 2006), and J. Rivoir, “Statistical Linearity Calibration of Time-to-Digital Converters Using a Free-Running Ring Oscillator”, 15th Asian Test Symposium (2006), wherein FIG. 2A shows the circuit configuration and FIG. 2B shows the time chart of the circuit operation.
As shown in FIG. 2A, the TDC has a first delay line in which a plurality of non-inverter buffers 14 that sequentially delay original clock CK by first predetermined delay amount τ1 is connected in series, a second delay line in which a plurality of non-inverter buffers 15 that sequentially delay signal to be measured SC by a second predetermined delay amount τ2 is connected in series, a plurality of flip-flops 16 that receive each of delayed clocks CK1, CK2, CK3, . . . , sequentially delayed in the first delay line as a data input and each of delayed signals SC1, SC2, SC3, . . . , sequentially delayed in the second delay line as a clock input, and an encoder circuit 17 that calculates the jitter of a signal to be measured with respect to clock CK from outputs Q1, Q2, Q3, . . . , of the plurality of flip-flops 16. First predetermined delay amount τ1 is greater than second predetermined delay amount τ2 (τ1>τ2). The number of connected non-inverter buffers 14 and 15 needs to be greater than or equal to a number calculated by dividing the expected magnitude of the jitter of signal SC to be measured by the difference between the delay amounts of non-inverter buffers 14 and 15 plus a predetermined margin.
As shown in FIG. 2B, delayed clocks CK1, CK2, CK3, . . . , output from each of non-inverter buffers 14 are delayed by τ1 from one another and delayed signals SC1, SC2, SK3, . . . to be measured, output from each of non-inverter buffers 15 are delayed by τ2 from one another. As described above, τ1>τ2, and therefore, even if CK1 rises prior to SC1, the difference between the timing of the CK rise and the timing of the SC rise becomes gradually smaller, and will change so that SC3 rises prior to CK3 in due course. In response to this, outputs Q1, Q2 of flip-flops 16 become “H”; however, outputs Q3, of flip-flops 16 after that become “L”. It is possible to detect the timing at which delayed signal SC to be measured rises prior to delayed clock CK by detecting the position at which the outputs of flip-flops 12 change using encoder circuit 17. In the configuration of the TDC in FIG. 2A, the time resolution in detection of jitter of signal SC to be measured is the difference between the delay amounts of non-inverter buffer 14 and non-inverter buffer 15. As a result, it is possible to measure jitter with a high resolution by appropriately selecting the delay amounts of non-inverter buffer 14 and non-inverter buffer 15.